1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication elevated source/drain regions on a staircase shaped insulating layer.
2) Description of the Prior Art
Field effect transistors (FETs) are comprised of a pair of diffusion regions, referred to as a source and a drain, spaced apart within a semiconductive substrate. Such include a gate provided adjacent the separation region and between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate area adjacent the gate and between the diffusion regions is referred to as the channel. The semiconductive substrate typically comprises a bulk monocrystalline silicon substrate having a light conductivity dopant impurity concentration. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material over an underlying insulating layer. Such are commonly referred to as semiconductor-on-insulator (SOI) constructions.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths greater than 2 microns) to short-channel devices (i.e., channel lengths less than 0.5 microns).
As field effect transistor channel lengths (i.e., gate widths) became smaller, so-called short channel effects began to become increasingly significant. As a result, device design and consequently process technology had to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example, as device dimensions are reduced and the supply voltage remains constant, the lateral electric field generated within the substrate increases. If the field becomes strong enough, it can give rise to so-called hot-carrier effects. This becomes a significant problem with channel lengths smaller than 0.5 microns. Hot-carrier effects cause unacceptable performance degradation in n-type transistor devices built with conventional drain structures if their channel lengths are less than 0.5 microns.
A preferred method of overcoming this problem is to provide lightly doped drain (LDD) regions within the substrate relative to the channel region in advance of the source and drain regions. The LDD regions are provided to be lighter conductively doped (i.e., less concentration) than the source and drain regions. This facilitates sharing of the voltage drop by the drain in the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD n-type transistors. The LDD regions absorb some of the voltage drop potential into the drain, thus effectively eliminating hot carrier effects. As a result, the stability of the device is increased.
However, further shrinking of the gate width (i.e., shorter channel length) makes the LDD region of a conventional transistor less effective. For example, shorter channel lengths require the LDD length to be reduced to ensure sufficient semiconductive material between the diffusion regions to prevent conductance when the gate voltage is off. One way of attending to such problems is to displace the predominant portion of the source and drain regions outwardly away from the substrate by elevating them. For example, a thin (e.g., 200-nm) epitaxial layer of monocrystalline silicon can be selectively grown from an exposed monocrystalline source and drain substrate areas within an epi reactor, and provided with sufficiently high conductivity doping to effectively provide source and drain regions. The lighter doped LDD regions can be provided within the substrate immediately below the elevated source and drain. Thus, a channel of sufficient length is effectively provided despite the smaller width gate.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,597,746 (Prall) that shows a FET with elevated S/D.
U.S. Pat. No. 5,683,924 (Chan et al. ) shows a raised S/D process.
U.S. Pat. No. 5,422,289 (Pierce) shows another raised poly S/D process.
U.S. Pat. No. 6,015,727 (Wanlass) teaches a damascene S/D process.
It is an object-of the present invention to provide a method for fabricating an elevated source/drain (S/D).
It is an object of the present invention to provide a method for fabricating an elevated source/drain (S/D) on a staircase shaped insulating layer.
To accomplish the above objectives, the present invention provides a method for fabricating a elevated source/drain (S/D) on a staircase shaped insulating layer. The invention has two preferred embodiments.
The first preferred embodiment can be described as follows. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and.hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source /drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
The second preferred embodiment is described as follows. An insulating layer having a staircase shaped opening is formed over the substrate. The staircase shaped opening comprised of a lower opening and an upper opening. Next, A gate dielectric layer and gate electrode layer are formed over the substrate filling the a staircase shaped opening. We pattern the gate dielectric layer and gate electrode layer to form a gate dielectric and gate electrode. Then ions are implanted into the substrate through said staircase opening to form LDD regions 128. Gate spacers are formed on the sidewalls of the gate electrode and insulating layer spacers on the sidewalls of the insulating layer in the staircase shaped opening . We form elevated source/drain (S/D) blocks in the staircase shaped opening. Ions are implanted into the elevated source drain (S/D) blocks to dope the elevated source drain (S/D) blocks. Silicide regions are formed on the gate and the elevated source/drain (S/D) blocks.
The invention has many advantages over the conventional method to form Source/drains. The invention reduces parasitic junction capacitance. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.